Hsinchu, Taiwan – M31 Technology Corporation (M31), a global silicon intellectual property (IP) provider, recently announced that the 12nm Digital PLL IP has completed chip validation and is ready for mass production. Meanwhile, the 7nm Digital PLL IP will also enter the tape-out stage for customers. Furthermore, M31 is actively advancing the development of 3nm process circuitry, which will provide fast locking functions in addition to the existing frequency hopping, spread spectrum, and dynamic sleep modes to meet the advanced process design needs of the high-end CPU/GPU market; at the same time, ensuring stability and reliability of clock signals to meet the diverse environment and applications.

With the rapid development of IoT applications, IoT devices need to have stable and accurate clock signals to ensure the accuracy of data transmission and communication. Battery life and switching efficiency are crucial for applications such as wireless sensor networks, smart homes, and wearable devices. Whereas PLL (Phase-Locked Loop), being the critical clock circuit in all digital applications, and the continuous reduction in size and improvement in performance is the key foundation to realize the next generation of technology. As a leader in high-speed transmission IP, M31 has developed the 12nm Digital PLL, which consumes only 1.1mW of power at an operating frequency of 3GHz. Through dynamic voltage frequency scaling techniques further reduce power consumption by more than 50%, making IoT devices more suitable for long operation times and low-power scenarios. On the other hand, the clock output of the 12nm Digital PLL IP meets the low-noise requirements of IoT sensors and leverages process advantages to provide ultra-low power consumption in an extremely compact area, making it the most competitive IP in the market. Compared to the limitations of using IO voltage in traditional PLL, Digital PLL offers chip designers more convenience in integration and achieves superior power consumption through the utilization of a digital circuit model and unique techniques to combat power noise, while the fast locking feature further enhances performance and brings lower latency in mode switching to the system.

With the increasing complexity of chip development, the highly functional and adaptable Digital PLL is undoubtedly playing a key role in advanced process SoC design, helping customers to realize various application scenarios that help improve the performance, efficiency, and reliability of IoT devices. M31’s 12nm Digital PLL IP features a single power supply and comprehensive Design-for-Testability (DFT) functionality, providing SoC integration advantages over traditional PLLs, while optimized noise immunity further ensures stable device operation in the presence of interference, and advanced features such as dynamic frequency conversion mode to meet the urgent need for clocking solutions for the IoT. M31 is currently committed to developing a 3nm process circuitry to further enhance product performance and power efficiency, which will enable Digital PLL IP to address more complex and demanding High-Performance Computing (HPC) as well as AI applications, providing customers with more competitive solutions.