PCIe 4.0 PHY and AXI Controller

The integrated solution for PCIe PHY IP and PCIe 4.0 with AXI Controller can be set as the physical layer of a PCIe 4.0 transceiver IP, supporting complete PCIe 4.0 base applications. The IP is compliant with the PIPE 4.4.1 specification, integrating high-speed mixed signal circuits to support 16Gbps PCIe 4.0 traffic, and is also backward compatible with existing PCIe 3.1, 2.1, and 1.1 at data rates of 8.0, 5.0, and 2.5 Gbps, respectively.
In addition, the controller provides a high-performance and user-friendly interconnect solution that bridges PCI Express with the latest iteration of the AXI protocol. Building upon the preceding generations of PCI Express interface IP, the PCIe controller fully leverages its leading-edge architecture and reliability. Besides, its AXI user interface incorporates built-in Direct Memory Access (DMA) functionalities, adhering to both the AMBA® AXI3 and AXI4 specifications.