Memory Compiler

M31 memory compilers are designed with high industrial standards to which provides the memory solutions for density, power, and performance optimizations. M31 memory compilers are using leveraging  industry-leading techniques to help customers to achieve their various SoC projects.
Meanwhile, M31 memory compiler IP was certified with ASIL-D of ISO 26262 in April, 2019.

Compiler Types

 

Compiler type

Features

Bit-cell

Synchronous Write-through

Power-gating

Scan; BIST interface

High density

SP-SRAM
  • Multi-bank structure
  • High density design

High density bit cell

(HD-6T)

Y / N

Y / N

Y / N

High speed

SP-SRAM
  • Multi-bank structure
  • High speed design

High current bit-cell

(HC-6T)

Y / N

Y / N

Y / N

1P register file
  • Single bank structure
  • High density design

 

HC-6T or HD-6T

Y / N

Y / N

Y / N

2P register file
  • Single bank structure
  • High density design

2-Port bit-cell 

(8T)

Y / N

Y / N

Y / N

Ultra-high density 2P
  • Single bank structure
  • High density design

High current bit-cell

(HC-6T)

Y / N

Y / N

Y / N

DP-SRAM
  • Multi-bank structure
  • High density design

Dual-port bit-cell

(DP-8T)

Y / N

Y / N

Y / N

 ROM

  • Non-volatile read only memory

  • VIA layer programmable

VIA

N

N

N

Cache instance

  • High speed for data access time

  • Reserve timeslots for data-operation

High current bit-cell

(HC-6T)

Y / N

N

Y / N

Instance Types

Product

Features

IP

Big Macro

  • High density macro

  • Provides multi redundancy (Yield/ Vmin compensation)

  • Provides multi-options for speed and yield/Vmin optimization

2Mb, 4Mb

Wide range VDD operation Memory

  • Low VDD operation (~0.6V)

  • DVFS technique

SP-SRAM, 1PRF, 2PRF, ROM

Optimized PPA (OPPA)

  • Special feature for memory instances optimization

  • Optimized setup/hold time

  • Optimized power/performance

  • Optimized the area/flexible for P&R

Cache instances
  • IP Product Lists
  • Features
  • M31 Foundation IPs at TSMC 12E Process
  • M31 Foundation IPs at TSMC 28HPC+ Process
  • M31 Foundation IPs at TSMC 28ESF3 Process
  • M31 Foundation IPs at TSMC 40LP Process
  • M31 Foundation IPs at TSMC 55LP Process
  • M31 Foundation IPs at TSMC 55ULP Process
  • M31 Foundation IPs at TSMC 55ULPEF Process
  • M31 Foundation IPs at PSMC 40L Process
  • M31 Foundation IPs at PSMC 90A Process
  • M31 Foundation IPs at HLMC 28HKC+ Process
  • M31 Foundation IPs at HLMC 28LP Process
  • M31 Foundation IPs at HLMC 40LP Process
  • M31 Foundation IPs at HLMC 55LP Process
  • M31 Foundation IPs at HLMC 55HR Process
  • M31 Foundation IPs at HHGrace 40LP Process
  • M31 Foundation IPs at HHGrace 55LP Process
  • M31 Foundation IPs at HHGrace 55EF Process
  • M31 Foundation IPs at HHGrace 110G Process
  • M31 Foundation IPs at HHGrace 115EF Process
  • M31 Foundation IPs at HHGrace 130EF Process
  • M31 Foundation IPs at SMIC 40LL Process
  • M31 Foundation IPs at SMIC 40ULP Process
More
  • High-sigma design for yield and performance optimization
  • Ultra-high-speed techniques for Cache implementation
  • Ultra-low-power circuits for mobile and AIoT devices
  • Ultra-high-density memory design for consumer solutions
  • Provides multi-port memory design for different processors application
  • Apply the Dynamic Voltage/Frequency scaling (DVFS) technique for users with multi-VDD domain
  • Specific option pins for dynamic/standby power gating
  • Porosity top metal lines structure to improve customer’s chip routability
  • Synchronous read/write operations
  • Different VT of periphery devices options
  • Flexible bank structure for performance and power optimization
  • Specialty power gating for performance and power optimization
  • Separate dual rail design of VCCA(array) and VCCP(periphery)
  • Separate read/write margin for sigma coverage design
  • Separate read/write-assist strength for different accumulated density applications
  • BIST [ON/OFF]; Scan [ON/OFF];
  • Provides row/col-redundancy [ON/OFF]Different VT of periphery devices options
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